Design of Low-Power ÷16/17 Prescaler Using Powerpc Flip-Flops
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Abstract: Pre-scalar, this is considered as the most critical block in the design of frequency conflation plays veritably important part, whenever we talk about high frequency operation. These blocks are used generally in PLLs for frequency conflation. Rigorous trials have proved that the major donation for power dispersion in ADPLL is because of pre-scalar block. Hence it becomes veritably pivotal to design the pre-scalar block with minimal power dispersion. In this paper we borrow a fashion of using Power PC flip-flop to design a divide by 16/17pre-scalar, which consumes veritably minimal power. The propound circuit operates up to 1 GHz consuming veritably lower power of 0749mW. The affair frequency is in the range of 50 MHz to 60 MHz. Low power peak by 16/17pre-scalar using Power PC flip bomb is proposed at 0.12 µm CMOS technology using BSIM4 model at a force of 1.2 V. The circuit is schematically vindicated in DSCH 3.8. The layout verification was carried out in Microwind2. From the simulation it was observed that veritably minimal power dispersion was attained with a minimal face area of 1875.9 µm2.
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