Development of Comparative Design of Reversible and Irreversible 32-BIT ALUs

As technology increases everyone wants more features with in a small size electronic gadget, to make them smaller, quicker, more compact and increasing integration density we need to decrease the size of the transistors but due to the decrease in size challenges like power efficiency and heat management becomes major concerns in VLSI design.

Traditionally we are using the irreversible gates in digital circuits but during digital operations input information losing which directly contributes the energy dissipation according to Landauer's principle. But Reversible gates make every output corresponds to unique input and prevents the information loss thereby reduces the power dissipation. In this work, we compared a 32-bit Arithmetic Logic Unit (ALU) designed with both irreversible logic gates and reversible ALU constructed with Peres gate.

The reversible design has a Quantum Cost of 384 and produces 128 garbage outputs. Both ALUs were coded in Verilog and implemented on Xilinx Artix-7 FPGA. We evaluated performance of ALUs based on theoretical metrics and actual hardware performance metrics. The reversible ALU shows a significant performance by reducing power dissipation to 70mW compared to the 211mW of the irreversible ALU.

However, its latency was slightly higher at 22.737 ns compared to irreversible design latency(20.214ns) due to the routing overhead. our analysis indicates that reversible logic is very fast in logic implementation but delay is mainly due to the routing overhead, in this case there were 128 garbage outputs on FPGA. This study demonstrates that reversible logic uses lower energy compared to conventional designs by careful handling of routing and I/O complexity.