Concept Paper on Design and Optimization of Energyefficient Architectures for Edge Computing
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Edge computing is now transforming how data is processed by shifting the computing devices closer to the source of data generation. Even though this transformation helps reduce latency and bandwidth consumption, it introduces a critical challenge. The edge devices operate with strict hardware constraints. The conventional microcontrollers such as ATmega328p and ESP32 offer simple and reliable design while they come with lack of architectural mechanism for advanced energy optimization.
This research proposes the idea of designing an edge oriented, System on Chip (SoC) implemented using Verilog, integrating a 32bit Reduce Instruction Set Computing V(RISC-V/ RV32I) core with essential peripherals for the proposed microcontroller design. The new architecture explores energy minimization strategies including Dynamic Voltage and Frequency Scaling (DVFS), Sleep Modes, Clock Gating, Approximate ALU (Arithmetic and Logic Unit) in a separate manner. All the techniques will be implemented and evaluated separately. After thorough evaluation all techniques will be synergized and evaluated in one system. By means of Xilinx Vivado simulation and power analysis, a structured experimental matrix compares the baseline design against the optimized variants mentioned above. To represent edge workloads an integer multiplication (N32/64) and FIR (Finite Impulse Response) filtering will be complied using RISCV32 GCC toolchain under Ubuntu Operating System and executed on the soft SoC. The estimations of power, latency and Hardware areas such as LUTSs (Look Up Tables), Registers, BRAM (Block Random Access Memory) will be measured and compared to evaluate energy, latency and area tradeoffs.
The study leverages recent research in energy efficient RISC-V microarchitectures, approximate computing and adaptive DVFS policies. This research contributes a reproducible methodology for architectural energy optimization in edge computing by providing a quantitative evaluation within a unified FPGA (Field Programmable Gate Array) based framework. The expected outcome is a demonstrable reduction is dynamic and static power while maintaining an acceptable performance degradation, setting up design guidelines for next generation energy-aware embedded architectures.
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