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Optimized 2/3 Prescaler Design Using Different Logic Families in 45nm CMOS Process

Authors

G. Vimala

Electronics and Communication Engineering, Bharath Institute of Higher Education and Research, Tambaram, Chennai (IN)

F. Vincy Lloyd

Electronics and Communication Engineering, Bharath Institute of Higher Education and Research, Tambaram, Chennai (IN)

Article Information

DOI: 10.51583/IJLTEMAS.2025.1408000043

Subject Category: VLSI

Volume/Issue: 14/8 | Page No: 361-364

Publication Timeline

Submitted: 2025-09-01

Published: 2025-09-01

Abstract

Abstract: Frequency division is a key application of flip-flops, particularly in wideband frequency synthesizers based on phase-locked loops (PLLs). In such systems, the high-frequency output from the voltage-controlled oscillator (VCO) is typically fed directly into a prescaler, also known as an N/N+1 counter, which serves as a critical building block. As semiconductor technology continues to scale down, both the channel length and supply voltage are significantly reduced. Consequently, the prescaler must operate reliably at higher frequencies and under lower voltage conditions.

Keywords

LT-Spice-IV, VCO (voltage-controlled oscillator), DMP (Dual Modulus Prescaler) TG (transmission gate), PTL (pass transistor logic).

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References

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